Production Ready

Register Generator for ASIC & FPGA

Generate production-ready SystemVerilog RTL, UVM RAL, C Headers, IP-XACT, SystemRDL & Documentation from a single register specification. Plus built-in Design Rule Checking and Diff & Impact Analysis — 100% offline.

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Windows

Download CLI

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Linux

Download CLI

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macOS

Download CLI

v1.1.0 — Released August 2026

✨Try Web App Version

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6 Output Formats

RTL, UVM RAL, C Header, IP-XACT, SystemRDL, Markdown — all from one spec

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Lint / DRC

12 ASIC-focused design rules catch silicon bugs before tape-out

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Diff & Impact

See exactly which RTL, UVM, C headers are affected by spec changes

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SoC Memory Map

Merge 50+ IP specs into a unified, conflict-free SoC memory map

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100% Offline

Standalone binary — no internet, no cloud, no security leaks

How It Works

RegGen compiles register specifications (YAML, JSON, IP-XACT, or SystemRDL) into 6 fully valid output targets in a single run. Select a tab below to see how a YAML specification compiles into different formats:

name: spi_ctrl
description: SPI Controller Register Block
baseAddress: 0x40000000
registers:
  - name: spi_ctrl
    description: "SPI Control Register"
    offset: 0x00
    fields:
      - name: enable
        description: "Enable the SPI peripheral"
        bitOffset: 0
        bitWidth: 1
        access: RW
        resetValue: 0
      - name: mode
        description: "Operating mode selection"
        bitOffset: 1
        bitWidth: 2
        access: RW
        resetValue: 0
  - name: spi_status
    description: "SPI Status Register"
    offset: 0x04
    fields:
      - name: busy
        description: "SPI Busy Flag"
        bitOffset: 0
        bitWidth: 1
        access: RO
        resetValue: 0
      - name: rx_fifo_empty
        description: "RX FIFO Empty"
        bitOffset: 1
        bitWidth: 1
        access: RO
        resetValue: 1

Supported Formats

RegGen accepts 5 input formats and generates 6 output targets. Mix and match — input in SystemRDL, output in IP-XACT. Input in Excel, output in RTL.

Input Formats

Format	Extension	CLI Flag	Description
YAML	`.yaml`, `.yml`	`--format yaml`	Human-friendly register specification
JSON	`.json`	`--format json`	Structured JSON register specification
IP-XACT	`.xml`	`--format ipxact`	IEEE 1685-2014 standard XML
SystemRDL	`.rdl`	`--format systemrdl`	Accellera SystemRDL 2.0 description
Excel	`.xlsx`	`--format excel`	Spreadsheet-based specification

Output Targets (all generated in a single run)

Output	File	Purpose
SystemVerilog RTL	`<block>_csr.sv`	Synthesizable CSR with address decoding, APB/AXI4-Lite interface
UVM RAL Model	`<block>_ral.sv`	Complete UVM Register Abstraction Layer
C Header	`<block>_regs.h`	Base addresses, offsets, bitmasks, shift macros
Documentation	`<block>_regs.md`	Markdown register manual with field tables
IP-XACT 2014	`<block>_ipxact.xml`	IEEE 1685-2014 for EDA interoperability
SystemRDL 2.0	`<block>.rdl`	Accellera SystemRDL for EDA flows

SoC Memory Map Merging

Modern SoCs have hundreds of nested IP blocks with complex bus bridges. The merge command ingests multiple IP register specs and merges them into a single, conflict-free top-level SoC memory map — with automatic namespace prefixing, address overlap detection, and unified output generation.

reg-gen merge -m soc_manifest.yaml -o ./soc_output -p APB

Example: SoC Address Map

0x40001000uart0(3 regs, uart_regs.yaml)

0x40002000uart1(3 regs, uart_regs.yaml)

0x40003000spi(2 regs, spi_regs.json)

0x50000000periph_bus.i2c(2 regs, i2c_regs.rdl)AHB-to-APB

0x50001000periph_bus.timer(3 regs, timer_regs.xml)AHB-to-APB

Key Capabilities

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Multi-Instance

Same IP at different base addresses

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Nested Hierarchy

Bus bridges with relative addressing

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Cross-Format

Mix YAML, JSON, RDL, XML in one manifest

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Conflict Detection

Address overlaps & name collisions flagged

Lint / Design Rule Checking

The lint command checks your register spec against 12 ASIC-focused design rules, catching common mistakes that cause silicon bugs, verification headaches, or poor documentation.

reg-gen lint -i spec.yaml

12 Lint Rules

ID	Rule	Severity	Edition	What It Checks
`L001`	addr-align	ERROR	Community	Register offset not word-aligned (mod 4)
`L002`	field-overlap	ERROR	Community	Two fields overlap in bit range
`L003`	reserved-gaps	WARN	Community	Undefined bit positions in a register
`L004`	name-convention	WARN	Community	Register/field names contain invalid characters
`L005`	wo-field	WARN	Community	Write-only fields can't be read back
`L006`	reset-ro-nonzero	INFO	Community	Read-only field with non-zero reset value
`L007`	addr-gap	WARN	Pro	Large address gaps between registers
`L008`	field-no-desc	INFO	Pro	Field missing a description
`L009`	reg-no-desc	INFO	Pro	Register missing a description
`L010`	single-bit-no-name	WARN	Pro	Single-bit field with generic name
`L011`	reset-mask	WARN	Pro	Reset value exceeds field bit width
`L012`	addr-dense	INFO	Pro	Register block >50% address space unused

# Filter by severityreg-gen lint -i spec.yaml --severity warning
# Strict mode (Pro)reg-gen lint -i spec.yaml --rules strict
# JSON output for CI/CD (Pro)reg-gen lint -i spec.yaml --json

Diff & Impact Analysis

When a chip spec changes at the last minute, engineers panic. The diff command compares two register specs semantically and shows exactly which RTL, UVM, C headers, and tests are affected — preventing broken regressions before tape-out.

reg-gen diff -a spec_v1.yaml -b spec_v2.yaml

10 Change Types Detected

Change	Severity	Description
register-removed	⛔ Breaking	Register deleted — RTL, UVM, C headers all affected
register-moved	⛔ Breaking	Register offset changed — address decoder, firmware affected
field-removed	⛔ Breaking	Field deleted — RTL write path, UVM, C macros affected
field-bits-changed	⛔ Breaking	Bit range changed — masks, shifts, RTL bit selects affected
field-access-changed	⛔ Breaking	Access type changed (e.g., RW→RO) — RTL write logic affected
register-added	✅ Non-breaking	New register added to spec
field-added	✅ Non-breaking	New field added to a register
field-reset-changed	✅ Non-breaking	Reset value changed
register-desc-changed	✅ Non-breaking	Register description updated
field-desc-changed	✅ Non-breaking	Field description updated

Impact Analysis (Pro)

For each change, the tool maps which output areas are affected:

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RTL

Address decoder, read/write mux, resets

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UVM RAL

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C Header

#define macros, offsets, bitmasks

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Docs

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IP-XACT

XML elements, address offsets

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SystemRDL

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Tests

Reset checks, access-type tests

# Cross-format diffreg-gen diff -a old.json -b new.rdl
# Markdown report (Pro)reg-gen diff -a v1.yaml -b v2.yaml -o report.md
# CI/CD gate (exit code 1 = breaking)reg-gen diff -a main.yaml -b pr.yaml || exit 1

How to Install

RegGen ships as a standalone binary — no Node.js, Python, or any runtime dependency. Download the binary for your platform, add it to your PATH, and start generating. Perfect for air-gapped secure labs.

Standalone Binaries (Recommended)

Download our packaged standalone executables. No runtime dependencies required — extract and add directly to your system path:

Quick Setup

# Linux / macOSchmod +x reg-gen && sudo mv reg-gen /usr/local/bin/
# Windows (PowerShell)Move-Item reg-gen.exe C:\Windows\System32\
# Verify installationreg-gen --version

💡 Alternative: If you have Node.js, you can also install via npm: npm install -g reg-gen-cli

Licensing

We offer flexible licensing depending on your use case. For production teams working on commercial silicon, a Pro license is required.

Community EditionFree

Ideal for evaluation, students, and open-source.

Generate up to 2 registers per block
All 5 input formats supported
6 lint rules (L001–L006), max 10 findings
Basic diff (max 2 registers compared)
SoC merge (max 3 IP blocks)
Full validation command
100% offline operation

Pro LicenseCommercial

For production ASIC/FPGA teams and design services.

Unlimited registers & address blocks
All 12 lint rules, unlimited findings
Full diff with impact analysis
Unlimited SoC merge (50+ IP blocks)
JSON output & Markdown reports
Rule presets (strict/relaxed)
Commercial support with SLA
No watermarks on generated code

📩 Contact Sales for Pro License

💡 Want to evaluate with your full IP block? Request a 30-day Pro trial — no credit card required.

🚀 Request Free 30-Day Trial

Pricing

Simple, transparent pricing for individuals, teams, and enterprises. All plans include the full Pro feature set — unlimited registers, all 12 lint rules, full diff with impact analysis, and unlimited SoC merge.

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Individual

$149 / year

Single seat license for freelancers, consultants, and solo designers.

Get Started

Team

$499 / year

Up to 5 seats. Perfect for design teams.

Additional seats: $79 / year each

Get Team License

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Enterprise

Custom

Unlimited seats, priority support, SLA, and custom integrations.

Contact Sales

All plans include a 30-day free trial — no credit card required. Need a quote for your procurement team? Request a formal quote →

CLI Reference

RegGen includes 5 CLI commands for complete register management:

# Generate all output targetsreg-gen generate -i spec.yaml -o ./output -p APB
# Validate spec structurereg-gen validate -i spec.yaml
# Lint for design rule violationsreg-gen lint -i spec.yaml
# Diff two specs with impact analysisreg-gen diff -a v1.yaml -b v2.yaml

# Merge IPs into SoC memory mapreg-gen merge -m soc_manifest.yaml -o ./soc_output

Command Options

Command	Key Options	Description
`generate`	`-i, -o, -p, -f, -z`	Compile spec → RTL, UVM, C, Docs, IP-XACT, SystemRDL
`validate`	`-i, -f`	Validate spec syntax and structure
`lint`	`-i, --severity, --rules, --json`	Design rule checking (12 rules)
`diff`	`-a, -b, -o, --json`	Semantic diff with impact analysis
`merge`	`-m, -o, -p, -z`	SoC memory map merging

For complete documentation, schema reference, and integration guides, visit: Documentation → · 📄 Download Full Reference (PDF)

Frequently Asked Questions

Yes. RegGen generates deterministic, synthesizable RTL from a validated specification. The generated code follows industry-standard patterns — address-decoded CSR blocks with proper reset logic, read-mux, and write-enable gating. Many teams run the output through their existing lint (Spyglass, HAL) and formal verification flows before tape-out. The tool itself also includes 12 built-in DRC checks to catch common register bugs early.

RegGen's code generators are deterministic and extensively tested — given a valid spec, the output is always correct by construction. Every field's bit-select, reset value, access policy, and address decode is derived directly from your specification with no inference or guessing. If you find a discrepancy, it's almost always a spec error — which is exactly what our validate and lint commands are designed to catch before generation.

Absolutely — RegGen was built for this. The standalone binary has zero network dependencies. No telemetry, no license servers, no cloud calls. Download the binary once, transfer it to your secure environment via USB or approved media, and it runs completely offline. Your register specs and generated IP never leave your machine.

Register maps contain highly proprietary IP — base addresses, field layouts, and access policies reveal your chip's architecture. Many ITAR/EAR-controlled and enterprise environments prohibit uploading designs to cloud APIs. RegGen processes everything locally — no network calls, no telemetry, no cloud dependencies. Your designs stay within your secure perimeter.

RegGen accepts 5 input formats: YAML, JSON, IP-XACT (.xml), SystemRDL (.rdl), and Excel (.xlsx). All formats are supported in both the CLI and web app. Format is auto-detected from the file extension, or can be specified manually with the --format flag.

Define a YAML manifest listing your IP blocks with base addresses and source spec files. RegGen resolves the hierarchy (including nested bus bridges), checks for address overlaps and name collisions, prefixes all registers with their namespace path (e.g., uart0_CTRL, periph_bus_i2c_STATUS), and generates a single unified output set — RTL, UVM, C headers — for your entire SoC.

RegGen is a standalone CLI that works in any CI/CD pipeline. Use 'reg-gen lint' as a pre-commit check, 'reg-gen diff' in pull request validation (exits with code 1 if breaking changes are found), and 'reg-gen generate' to auto-rebuild outputs on spec changes. Pro users get JSON output for machine-readable CI integration.

Community edition is fully functional but limited: 2 registers per block, 6 lint rules (max 10 findings), basic diff (max 2 registers), and 3 IP blocks for SoC merge. Pro removes all limits — unlimited registers, all 12 lint rules, full impact analysis, JSON/Markdown reports, and no watermarks on generated code. Perfect for evaluation vs. production use.